Newsgroup: comp.lang.c++

Alf P. Steinbach wrote:
> * Michiel.Salters@tomtom.com:
>> Diomidis Spinellis wrote:
>>> seannakasone@yahoo.com wrote:
>>>> Is there a way to get the callstack level in c++?  for example, take
>>>> the following code:
>>
>>> If you're not interested in a precise number, but can accept a measure
>>> that would indicate the stack depth in bytes you can obtain the address
>>> of one of the function's plain local variables through the & operator
>>> and cast it to a char * pointer.  I've used this technique to track the
>>> use of stack space during the runtime of a program; see the snapshots at
>>> <http://www.spinellis.gr/codequality/stack.gif?clcpp>.  This technique
>>> is not portable, but will work on most computer architectures.
>>
>> The Itanium of course being one of those where it doesn't work; it has
>> two
>> stacks. C++ doesn't care; you can still implement Standard C++ on it.
>> Yet such features explain why Standard C++ doesn't have "a" callstack
>> level; it doesn't really make sense.
> 
> Although a bit off-topic, would you care to elaborate?  It's a long time 

My understanding is that the Itanium has SPARC-like register windows 
backed by a hardware assisted so-called register stack engine (RSE). 
When a function calls another arguments are placed into the general 
purpose registers Gr32-Gr128.  Through an alloc instruction the called 
function specifies the layout of its stack frame (input registers, local 
registers, and output registers).  This has the effect of mapping the 
calling function's output registers to the called function's input 
registers, and thus passing the function arguments through the registers 
without any overhead. The registers get renamed at the point of the 
call, so that all functions will always see their registers starting at 
Gr32.  When the 96 general purpose registers used for implementing the 
scheme run out, a spill will burst-write registers to the special 
register stack; later when the stack is unwound a fill will read the 
contents back from memory.

Why are two stacks needed?  My guess is that it was simpler to optimize 
the RSE hardware (for example caching or the burst mode alignment 
requirements) if the return addresses and the normal stack push/pop 
instructions didn't interfere with the register spill stack.

You can find a few more details in this article: 
http://www.intel.com/cd/ids/developer/asmo-na/eng/20314.htm?page=1

-- 
Diomidis Spinellis
Code Quality: The Open Source Perspective (Addison-Wesley 2006)
http://www.spinellis.gr/codequality?clcpp

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